By Junjie Wu, Lian Li
This ebook constitutes the refereed lawsuits of the eleventh Annual convention on complex desktop structure, ACA 2016, held in Weihai, China, in August 2016.
The 17 revised complete papers offered have been conscientiously reviewed and chosen from 89 submissions. The papers tackle matters akin to processors and circuits; excessive functionality computing; GPUs and accelerators; cloud and information facilities; power and reliability; intelligence computing and cellular computing.
Read or Download Advanced Computer Architecture: 11th Conference, ACA 2016, Weihai, China, August 22-23, 2016, Proceedings PDF
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Additional info for Advanced Computer Architecture: 11th Conference, ACA 2016, Weihai, China, August 22-23, 2016, Proceedings
Table 1. The parameters for multi-retention STT-RAM cells. 2 A Novel Hybrid Last Level Cache 33 From Table 1, it can be seen that the performance varies with different retention time. LRS’s access speed is even better than SRAM, while HRS’s write latency is longer than 10 ns. 2 Hybrid LLC Architecture In previous section, we get their overall performance of LRS, MRS and HRS cells. We ﬁnd that LRS owns the fastest access speed, so if we adopt LRS to design LLC, the LLC’s performance can be enhanced signiﬁcantly.
28–39, 2016. 1007/978-981-10-2209-8_3 A Novel Hybrid Last Level Cache 29 the microprocessor’s overall power consumption, therefore, researchers are focusing on alternative substitutes for SRAM. Spin-transfer torque random access memory (STT-RAM) is regarded as the most promising replacement for SRAM because it has almost all desired characters of the universal memory and cache, such as high storage density, fast read access speed and non-volatility. However, we are faced with two drawbacks of STT-RAM, namely, long write latency and high write energy, which result in the reduction of system performance and the enhancement of dynamic power consumption.
1. 5D-stacked products have already emerged [6, 7]. 5D stacking technology is the integration of memory (DRAM) with a multi-core processor. Larger capacities and higher bandwidth for in-package memory can be offered by the silicon interposer, as it has enough areas for much memory to be integrated and many thousands of connections available across the interposer. The interposer memory stacking also requires large bandwidth for processor-to-memory trafﬁc. In order to continuously increase the bandwidth, previous work [8, 9] shows that signiﬁcant routing resources inside the silicon interposer can be exploited to implement an additional network.
Advanced Computer Architecture: 11th Conference, ACA 2016, Weihai, China, August 22-23, 2016, Proceedings by Junjie Wu, Lian Li